Design and Implementation of an Efficient Vedic Multiplier for High Performance and Low Power Applications

This paper describes the work done towards design and implementation of multiplier modules using high speed architectures based on the concept of Vedic Mathematics. Unlike other Vedic multipliers where entire architecture is based on generating partial products in parallel and adding them, here the partial products for top level entity are adjusted using concatenation operation and are added using single carry save adder. However other entities are based on parallel partial product generation and adding using carry skip technique. This method allows for optimization in terms of speed and total thermal power dissipation. Additionally the multiplier module designed using carry look ahead adder is also presented which also allows for optimization between speed and area. The proposed designs are realized using ALTERA Cyclone – V FPGA.